Empirical and Statistical Application Modeling Using On-chip Performance Monitors

ions are estimated resulting in execution time estimates fairly close to the genuine architecture. Many times trace-driven simulations accept compiled execution traces. These are particularly used for determining features of next generation architectures that use the same instruction set architecture. Direct simulation involves a gate-level simulation of architecture (usually in some kind of hardware design language). Obviously, direct simulations are typically orders of magnitudes slower than their trace-driven counterparts. Architectural development these days typically involves iterative versions of trace-driven simulation for evaluating architectural tradeoffs [21, 28-30, 44]. As mentioned, trace-driven simulations became common in the mid-to-late 1970s [43]. The idea was to model performance while sacrificing some accuracy and reducing completion time. Studies regarding accuracy and usability have been numerous, as trace-driven simulators have continued to be popular methods of architectural performance evaluation [45-49]. Two recently successful trace-driven simulators are SimpleScalar [50] and MINT [51].